Seminar Report P Soc 5
P SoC A Accessory Study SEMINAR REPORT Submitted in apportioned accomplishment of the claim for the accolade of amount of Bachelor of Technology in ELECTRONICS AND COMMUNICATION ENGINEERING of MAHATMA GANDHI UNIVERSITY By JINJU P. K (65232) Department of Electronics and Advice Engineering Rajagiri School of Engineering and Technology Rajagiri Valley, Cochin - 682 039 2010-2011 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CERTIFICATE Certified that the academy presented blue-blooded “ PSoC-A Accessory Study” is a bonafide abode of the academy done by JINJU.
P. K (65232) of eighth division Electronics and Advice Engineering in apportioned accomplishment of the claim for the accolade of amount of Bachelor of Technology in Electronics and Advice of the Mahatma Gandhi University, Kottayam, during the bookish year 2010-2011. Activity Guide Head of the Department RONI ANTONYASHA PANICKER Centralized ExaminerExternal Examiner Place : Kakkanad Date : ACKNOWLEDGEMENT
To discover, assay and to present article new is to chance on an alien aisle appear and adopted destination is an backbreaking chance unless one gets a authentic torchbearer to appearance the way. I would accept never succeeded in commutual my assignment afterwards the cooperation, advance and advice provided to me by assorted people. Words are generally too beneath to accede my abysmal regards. I booty this befalling to authentic my abstruse faculty of acknowledgment and account to all those who helped me through the continuance of this project. I accede with acknowledgment and abasement my acknowledgment to Mr.
Rony Antony , Lecturer, Electronics & Advice Department, RSET, beneath whose advice I had the advantage to complete this project. I ambition to authentic my abysmal acknowledgment appear him for accouterment alone advice and abutment throughout the activity work. I back my aboveboard acknowledgment to Asha Paniker , Professor & Head of Electronics & Advice Department, RSET for her advance and cooperation. I would additionally like to acknowledge all agents associates and my co-students who were consistently there at the charge of the hour and provided with all the advice and facilities, which I appropriate for the achievement of my project.
My greatest acknowledgment are to all who admired me success abnormally my parents. Above all I cede my acknowledgment to the Almighty who bestowed self-confidence, adeptness and backbone in me to complete this assignment for not absolution me bottomward at the time of crisis and assuming me the argent lining in the aphotic clouds. ABSTRACT With a altered arrangement of configurable agenda and analog blocks, the Programmable System-on-Chip (PSoC) is a authentic system-levelsolution, alms a avant-garde adjustment of arresting acquisition, processing, and ascendancy with aberrant accuracy, aerial bandwidth,and above flexibility.
Its analog adequacy ps the ambit from thermocouples (DC voltages) to accelerated signals. Designerscan calmly actualize systemlevel designs, appliance a affluent library of prebuilt components, or custom verilog, and a schematic admission apparatus that uses the accepted architectonics blocks. This academy is based on the analog , agenda , affairs and alter subsystems ofPsoC 5 device. . CONTENTS 1. INTRODUCTION02 2. BLOCK DIAGRAM03 3. HARDWARE IMPLEMENTATION04 4. 1 IR TRANSMITTER CIRCUITRY……………………………………. 04 4. 2 IR SENSOR CIRCUITRY07 4. 3 CIRCUIT DIAGRAMS15 4. SOFTWARE IMPLEMENTATION17 5. 4 MPELAB IDE17 . 5 PROGRAM25 5. PCB DESIGN28 5. 1 PCB SCHEMATIC…………………………………………………….. 28 5. 2 PCB BOARD…………………………………………………………... 29 6. RESULS & CONCLUSION31 7. REFERENCES32 APPENDIX 1. INTRODUCTION With a altered arrangement of configurable agenda and analog blocks, the Programmable System-on-Chip is a authentic systemlevel solution, alms a avant-garde adjustment of arresting acquisition, processing, and ascendancy with aberrant accuracy, aerial bandwidth, and above flexibility. Its analog adequacy ps the ambit from thermocouples (DC voltages) to accelerated signals. PSoC 5 (CY8C55xxx, CY8C54xxx, CY8C53xxx,
CY8C52xxx) families are absolutely scalable 8-bit and 32-bit PSoC belvedere accessories that allotment these characteristics: ¦ Absolutely pin, borderline accordant ¦ Aforementioned chip development ambiance software ¦ Aerial performance, configurable agenda arrangement that supports a avant-garde ambit of advice interfaces, such as USB, I2C, and CAN ¦ Aerial precision, aerial achievement analog arrangement with up to 20-bit ADC, DACs, comparators, opamps, and programmable blocks to actualize PGAs, TIAs, mixers, etc. ¦ Calmly configurable argumentation arrangement ¦ Adjustable acquisition to all pins ¦ Aerial performance, 8-bit single-cycle 8051 (PSoC 3) or 32-bit ARM Cortex-M3 (PSoC 5) amount . 1 OBJECTIVE * 8051 or Cortex-M3 Central Processing Assemblage (CPU) with a nested vectored arrest ambassador and a aerial achievement DMA ambassador * Several types of anamnesis elements including SRAM, flash, and EEPROM * Arrangement affiliation features, such as clocking, a featurerich ability system, and able programmable inputs and outputs 2. TOP LEVEL ARCHITECTURE 2. 1 CPU SYSTEM 2. 1. 1 PROCESSOR The PSoC 5 CPU subsystem is congenital about a 32-bit three date pipelined ARM Cortex-M3 processor animate up to 80 MHz. The PSoC 5 apprenticeship set is the aforementioned as the Thumb-2 apprenticeship set accessible on accepted Cortex- M3 devices.
Three date pipelining operating at 1. 25 DMIPS/MHz. This helps to admission beheading acceleration or abate power. * Supports Thumb-2 apprenticeship set: * The Thumb-2 apprenticeship set supports circuitous operations with both 16- and 32-bit instructions * Atomic bit akin apprehend and abode instructions * Abutment for aloof anamnesis admission * Improved cipher density, ensuring able use of memory. * Easy to use, affluence of programmability and debugging: * Ensures easier clearing from 8- and 16-bit processors * Nested Vectored Arrest Ambassador (NVIC) assemblage to abutment interrupts and exceptions: * Helps to accomplish accelerated arrest acknowledgment Extensive alter abutment including: * Serial Wire Alter Port (SWD-DP), Serial Wire JTAG Alter Port (SWJ-DP) ? Break credibility ? Beam appliance ? Apprenticeship archetype ? Cipher archetype 2. 1. 2 INTERRUPT CONTROLLER The CPU subsystem includes a programmable Nested Vectored Arrest Ambassador (NVIC), DMA (Direct Anamnesis Access) controller, Beam accumulation ECC, and RAM. The NVIC of both PSoC 3 and PSoC 5 accessories provides low cessation by acceptance the CPU to agent anon to the aboriginal abode of the arrest account routine, bypassing the jump apprenticeship appropriate by alternative architectures. The PSoC 5 arrest ambassador additionally offers a few avant-garde nterrupt administration capabilities, such as arrest appendage chaining to advance assemblage administration with assorted awaiting interrupts accouterment lower latency. Supports 32 arrest curve * Programmable arrest agent * Configurable antecedence levels from 0 to 7 * Abutment for activating change of antecedence levels * Abutment for alone enable/ attenuate of anniversary arrest * Nesting of interrupts * Assorted sources for anniversary arrest band (can be either anchored function, UDB, or from DMA) * Supports both akin activate and beating activate * Appendage chaining, backward arrivals and exceptions are authentic in PSoC® 5 accessories 2. 1. DMA CONTROLLER The DMA ambassador allows peripherals to barter abstracts afterwards CPU involvement. This allows the CPU to run slower, save power, or use its cycles to advance the achievement of firmware algorithms. * Uses the PHUB for abstracts alteration * Includes 24 DMA channels * Includes 128 transaction descriptors (TD) * Eight levels of antecedence per approach * Affairs can be adjourned or canceled * Anniversary transaction can be from 1 to 64 KB * Large affairs can be burst into abate bursts of 1 to 127 bytes. * Anniversary approach can be configured to accomplish an arrest at the end of alteration 2. 1. 4 CACHE CONTROLLER
In PSoC 5 devices, the beam accumulation additionally reduces arrangement ability burning by abbreviation the abundance with which beam is accessed. The processor acceleration itself is configurable acceptance for animate ability burning acquainted for specific applications. * Apprenticeship accumulation * Absolute mapped * 128 bytes absolute accumulation anamnesis * Registers for barometer accumulation hit/miss ratios * Absurdity alteration cipher (ECC) abutment * Absurdity logging and arrest bearing * Designed to put beam into beddy-bye automatically to save ability 2. 2 MEMORY The PSoC nonvolatile subsystem consists of Flash, bytewritable EEPROM, and nonvolatile agreement options.
The CPU can reprogram alone blocks of Flash, enabling cossack loaders. An Absurdity Acclimation Cipher (ECC) can accredit aerial believability applications. A able and adjustable aegis archetypal allows the user to selectively lock blocks of anamnesis for apprehend and abode protection, accepting acute information. The byte-writable EEPROM is accessible on-chip for the accumulator of appliance data. Additionally, called agreement options, such as cossack acceleration and pin drive mode, are stored in nonvolatile memory, acceptance settings to become animate anon afterwards ability on displace (POR). 2. 2. 3 NON VOLATILE LATCH
A Nonvolatile Latch (NVL or NV latch) is an arrangement of programmable, nonvolatile anamnesis elements whose outputs are abiding at low voltage. It is acclimated to configure the accessory at Ability on Reset. Anniversary bit in the arrangement consists of a airy latch commutual with a nonvolatile cell. On POR absolution nonvolatile corpuscle outputs are loaded to airy latches and the airy latch drives the achievement of the NVL. FEATURES * A 4x8-bit NV latch for accessory agreement * A 4x8-bit Abode Once NV latch for accessory aegis 2. 2. 4 SRAM PSoC® 3 and PSoC® 5 accessories accommodate on-chip SRAM. These families action accessories that ambit from 2 to 64 kilobytes.
PSoC 3 accessories action an added 4 kilobytes as a trace buffer. * Organized as up to three blocks of 4 KB each, including the 4 KB trace buffer, for CY8C38 family. * Organized as up to 16 blocks of 4 KB each, for CY8C55 family. * Cipher can be accomplished out of portions of SRAM, for CY8C55 family. * 8-, 16-, or 32-bit accesses. In PSoC 3 accessories the CPU has 8-bit absolute admission to SRAM. * Zero delay accompaniment accesses. * Arbitration of SRAM accesses by the CPU and the DMA controller. * Altered blocks can be accessed accompanying by the CPU and the DMA controller. 2. 2. 5 FLASH PROGAMMING MEMORY
PSoC 3 and PSoC 5 accommodate on-chip Beam memory. These two families action accessories that ambit from 16 to 256 kilobytes. Added Beam is accessible for either absurdity alteration bytes or abstracts storage. PSoC 3 and PSoC 5 Beam anamnesis accept the afterward features: * Organized in rows, area anniversary row contains 256 abstracts bytes additional 32 bytes for either absurdity acclimation codes (ECC) or abstracts storage. * For PSoC 3 architecture: CY8C38 Family, organized as one block of 64, 128, or 256 rows. * For PSoC 5 architecture: CY8C55 Family, organized as either one block of 128 or 256 rows, or as assorted blocks of 256 rows each. Stores CPU affairs and aggregate or nonvolatile abstracts * For PSoC 5 architecture: CY8C55 Family, 8-, 16-, or 32-bit apprehend accesses. PSoC 3 architectonics has alone 8-bit absolute access. 2. 2. 6 EEPROM PSoC 3 and PSoC®5 accessories accept on-chip EEPROM memory. These two families action accessories that ambit from 512 bytes to 2 kilobytes. * PSoC 3 and PSoC 5 EEPROM anamnesis accept the afterward features: * Organized in rows, area anniversary row contains 16 bytes * Organized as one block of 32, 64, or 128 rows, depending on the accessory * Stores nonvolatile abstracts * Abode and abolish appliance SPC commands Byte apprehend admission by CPU or DMA appliance the PHUB * Programmable with a simple command/status annals interface EEPROM anamnesis provides nonvolatile accumulator for user data. EEPROM abode and abolish operation is done appliance SPC commands. It may be apprehend by both the CPU and the DMA controller, appliance the PHUB. All apprehend accesses are 8-bit. 2. 2. 7 EMIF PSoC 3 and PSoC 5 architectures accommodate an alien anamnesis interface (EMIF) for abutting to alien anamnesis accessories and borderline devices. The affiliation allows apprehend and abode admission to the devices.
The EMIF operates in affiliation withUDBs, I/O ports, and alternative PSoC 3 and PSoC 5 apparatus to accomplish the all-important address, data, and ascendancy signals. The EMIF does not ambush abode abstracts amid the PHUB and the I/O ports. It alone generates the appropriate ascendancy signals to latch the abode and abstracts at the ports. The EMIF generates a alarm to run alien ancillary and asynchronous memories. It can accomplish four altered alarm frequencies, which are the bus alarm disconnected by 1, 2, 3, or 4. The EMIF supports four types of alien memory: ancillary SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR Flash.
External anamnesis can be accessed via the 8051 xdata amplitude or the ARM Cortex-M3 alien RAM space; up to 24 abode $.25 can be used. The anamnesis can be 8 or 16 $.25 wide. 2. 3 SYSTEM WIDE RESOURCES 2. 3. 1 CLOCKING SYSTEM The alarm arrangement has these: * Four centralized alarm sources admission arrangement integration: * 3 to 67 MHz Centralized Main Oscillator (IMO) ±1% at 3 MHz * 1 kHz, 33 kHz, 100 kHz Centralized Low Acceleration Oscillator (ILO) outputs * 12 to 67 MHz alarm doubler output, sourced from IMO, MHz Alien Clear Oscillator (MHzECO), and Agenda Arrangement * Interconnect (DSI) 24 to 67 MHz apportioned Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI * DSI arresting from an alien I/O pin or alternative argumentation as able-bodied as a alarm antecedent * Two alien alarm sources accommodate aerial attention clocks: * 4 to 33 MHz Alien Clear Oscillator (MHzECO) * 32. 768 kHz Alien Clear Oscillator (kHzECO) for Real Time Alarm (RTC) * Committed 16-bit affiliate for bus alarm Eight alone sourced 16-bit alarm dividers for the agenda arrangement peripherals * Four alone sourced 16-bit alarm dividers for the analog arrangement peripherals * IMO has a USB approach that auto locks to the USB bus clock, acute no alien clear for USB. (USB able genitalia only) 2. 3. 2 POWER SUPPLY AND MONITORING PSoC 3 and PSoC 5 accessories accept abstracted alien analog and agenda accumulation pins, labeled appropriately Vdda and Vddd. The accessories accept two centralized 1. 8V regulators that accommodate the agenda (Vccd) and analog (Vcca) food for the centralized amount logic.
The achievement pins of the regulators (Vccd and Vcca) accept actual specific capacitor requirements that are listed in the datasheet. These regulators are available: * Analog regulator for the analog area accumulation * Agenda regulator for the agenda area accumulation * Beddy-bye regulator for the beddy-bye area * I2C regulator for powering the I2C argumentation * Hide regulator for bartering accumulate animate ability for accompaniment assimilation during hide 2. 3. 3 WATCH DOG TIMER The Babysitter Timer (WDT) ambit automatically reboots the arrangement in the accident of an abrupt beheading path. This timer charge be serviced periodically.
If not, the CPU resets afterwards a defined aeon of time. Once the WDT is enabled it cannot be disabled except during a displace event. This is done to anticipate any aberrant cipher from disabling the WDT displace function. To use the WDT function, the user is appropriate to accredit the WDT action during their startup code. The WDT has the afterward features: * Aegis settings to anticipate adventitious bribery of the WDT * Optionally-protected application (feeding) of the WDT * A configurable low ability approach to abate application requirements during beddy-bye approach * A cachet bit for the babysitter accident that shows the cachet alike afterwards a babysitter displace 2. . 4RESET POWER ON RESET Ability on Displace (POR) is provided primarily for a arrangement displace at ability up. The IPOR will authority the accessory in displace until all four voltages; Vdda, Vcca, Vddd, Vccd, are to datasheet specification. The POR activates automatically at ability up and consists of: An estimated POR (IPOR) – is acclimated to accumulate the accessory in displace during antecedent ability up of the accessory until the POR can be activated A attention POR (PRES) – acquired from a ambit calibrated for a actual authentic area of the POR cruise point. The ability on RESET clears all the displace cachet registers WATCHDOG RESET
Watchdog Displace (WRES) detects aberrant cipher by causing a displace if the babysitter timer is not austere aural the userspecified time limit. The user charge consistently set the WRES initialization code. This was done to acquiesce the user to dynamically accept whether or not to accredit the babysitter timer SOFTWARE INITIATED RESET Software Initiated Displace (SRES) is a apparatus that allows a software-driven reset. The RESET_CR2 annals armament a accessory displace back a 1 is accounting into bit 0. This ambience can be fabricated by firmware or with a DMA. The RESET_SR0  cachet bit becomes set on the accident f a software reset. This bit charcoal set until austere by the user or until a POR reset. EXTERNAL RESET Alien Displace (XRES_N) is a user-supplied displace that causes actual arrangement displace back asserted. XRES_N is accessible on a committed pin on some devices, as able-bodied as a aggregate GPIO pin P1 on all devices. The aggregate pin is accessible through a customer-programmed NV Latch ambience and supports low pin calculation genitalia that don't accept a committed XRES_N pin. This aisle is about configured during the cossack appearance anon afterwards ability up. 3. CONCLUSION
Order a unique copy of this paper