Comparative Study of 6T and 8T SRAM Using Tanner Tool

  • Rajnarayan Sharma, Ravi Antil, Jonish

Abstract— in this cardboard we focus on the activating ability amusement during the Address operation in CMOS SRAM cell. The charging and absolution of bit curve absorb added ability during the Address “1” and Address “0” operation. 8T SRAM corpuscle includes two added aisle transistors in the cull bottomward aisle for able charging and absolution the bit lines. The after-effects of 8T SRAM corpuscle are taken on altered frequencies at ability accumulation of 1.5 V. The ambit is characterized by application the 130 nm technology which is accepting accumulation voltage of 1.5 V. Finally the after-effects are compared with Accepted 6T SRAM cell. The ability blown in low ability 8T SRAM corpuscle is reduced in allegory to accepted 6T SRAM cell. The aftereffect of the assay has activated advertence bulk for added study.

Keywords—SRAM, Tanner Tool, T-Spice, W-EDIT, IEEE


SRAM is mainly acclimated for the accumulation anamnesis in Microprocessors, mainframe computers, engineering workstations and anamnesis in duke captivated accessories due to High acceleration and low ability consumption. The allegation for low-power architectonics is adequate a aloft affair in high-performance agenda systems such as microprocessors [1], Agenda Arresting Processors (DSPs) and alternative applications. The accretion Bazaar of adaptable accessories and array powered carriageable cyberbanking systems is creating demands for chips that absorb the aboriginal accessible bulk of power. SRAM abide of about 60% of Actual Ample Calibration Integrated (VLSI) circuits. It is additionally said that memories are the better culprit for the ability amusement in any agenda arrangement and No agenda arrangement gets complete after memories.

Several techniques accept been proposed to abate the ability burning during Address operation of SRAM like, Segmented Basic Arena Architectonics for Low-Power Embedded SRAM [2], Low ability SRAM architectonics application half-swing beating approach techniques [3] and A single-bit band cross-point corpuscle activation (SCPA) architectonics for ultra-low ability SRAM’s[4].Some alternative techniques which are use for low ability SRAM like Half-Swing Pulse-Mode Techniques[5] these techniques are use for abate the ability amusement of the SRAM circuit. All these discussed affidavit are acclimated added chip for abbreviation the ability consumption.

In this cardboard optimized SRAM corpuscle contains two added appendage transistors in the pull-down aisle of the corresponding inverter to abstain charging of the bit-lines. These two aisle transistor are controlled by an added arresting address baddest (WS). During apprehend or address approach at atomic one of the appendage transistor allegation be angry OFF to abstract the active aisle of corresponding inverters.


Karimi and Alimoradi [6]: Rapid advance in semiconductor technology has led to shrinking of affection sizes of transistors application abysmal submicron (DSM) process. As MOS transistors admission abysmal submicron sizes, abominable after-effects apropos ability burning arise. This can be done by application one PMOS transistor and one NMOS transistor in alternation with the transistors of anniversary argumentation block to actualize a basic arena and a basic ability supply. Notice that in convenance alone one transistor is necessary, because of their lower on-resistance, NMOS transistors are usually used.

Cheng and Huang [7]: they present a low-power SRAM architectonics with quiet-bit band architectonics by accumulation two aloft techniques. Firstly, the authors use a one-side active arrangement for the address operation to anticipate the boundless full-swing charging on the bit lines. Secondly, they use a precharge chargeless affairs arrangement for the apprehend operation so as to accumulate all bit curve at low voltages at all times. SPICE simulation on a 2K-bit SRAM macro shows that such architectonics can advance to a cogent 84.4% ability abridgement over a self-designed baseline low-power SRAM macro.

Ming et. Al. [8]: They describes a low-power address arrangement by adopting allegation administration technique. By abbreviation the bitlines voltage swing, the bitlines activating ability is reduced. The anamnesis cell’s changeless babble allowance (SNM) is discussed to prove it is a achievable scheme. Simulation after-effects appearance analyze to accepted SRAM, in address aeon this SRAM saves added than 20% activating power.


SRAM or Changeless accidental Admission anamnesis is a anatomy of semiconductor anamnesis broadly acclimated in electronics, chip and accepted accretion applications. This anatomy of semiconductor anamnesis assets its name from the actuality that abstracts is captivated in there in a changeless fashion, and does not allegation to be dynamically adapted as in the case of DRAM memory. While the abstracts in the SRAM anamnesis does not allegation to be active dynamically, it is still volatile, acceptation that back the ability is removed from the anamnesis device, the abstracts is not held, and will disappear. There are two key appearance to SRAM – Changeless accidental Admission Memory, and these set it out adjoin alternative types of anamnesis that are available: The abstracts is captivated statically: This agency that the abstracts is captivated in the semiconductor anamnesis after the allegation to be active as continued as the ability is activated to the memory. SRAM is a anatomy of accidental admission memory: A accidental admission anamnesis is one in which the locations in the semiconductor anamnesis can be accounting to or apprehend from in any order, behindhand of the aftermost anamnesis area that was accessed. Fig 1 shows the read/write operations of an SRAM. To baddest a cell, the two admission transistors allegation be “on” so the elementary corpuscle (the flip-flop) can be affiliated to the centralized SRAM circuitry.

Fig. 1 Read/Write Operations

OPTIMIZED 8T SRAM CELL Schematic of 8T SRAM corpuscle is apparent in fig 2 In that we are application two added transistors M7 and M8 for abbreviation the ability dissipation. WS arresting is acclimated for authoritative the M7 and M8 during Address “0” and address “1” operation.

Fig. 2 Optimized 8T SRAM Cell


This area provides the detail simulation assay of Low ability SRAM corpuscle for altered frequencies. The activating ability may be bidding as: P=αCVf.


Fig. 3 Accepted 6T SRAM Corpuscle (S-EDIT)

Fig. 4 Optimized 8T SRAM Corpuscle (S-EDIT)


Fig. 5 Simulation Waveform of 6T SRAM at 1GHz (S-EDIT)

Fig. 6 Simulation Waveform of 8T SRAM at 1GHz (S-EDIT)

From the fig 4.7 it has been bright that for 1 GHz the charging time is beneath again absolution time. So due to accession in charging and absolution time with abundance the ability amusement will additionally increase.

Fig. 7 Simulation Waveform of 6T SRAM at 2GHz (S-EDIT)

Fig. 8 Simulation Waveform of 8T SRAM at 2GHz (S-EDIT)




Power Amusement in 6T SRAM corpuscle (µw)

Power Amusement in 8T SRAM corpuscle (µw)

1 GHz



2 GHz



Write operation on altered frequencies, are accustomed in Table I. Our 8T SRAM corpuscle dissipates lower activating ability during the switching activity. In 8T SRAM corpuscle the crosstalk voltage ethics are added for bit lines, chat band (WL) and for outputs in allegory to accepted SRAM corpuscle but these Ethics can be controlled with the advice of able allocation of Width (W) and Length (L) of the transistor.


Fig. 9 Simulation Waveform of 6T SRAM (S-EDIT)

Fig. 10 Simulation Waveform of 8T SRAM (S-EDIT)



Different SRAM cells

Average Ability Dissipation



6.75 µw

5.44 ns


5.52 µw

3.86 ns

In our 8T SRAM corpuscle as apparent aloft we are preventing any distinct bit band from actuality absolved during address “0” as able-bodied as address “1” approach by able alternative of arresting WS, which about-face either M7 or M8 OFF. The allegory of accepted 6T SRAM corpuscle and 8T SRAM corpuscle is apparent in table II


Most of the developed low-power SRAM techniques are acclimated to abate alone apprehend power. Since, in the SRAM cell, the address ability is about beyond than apprehend power. We accept proposed an SRAM corpuscle to abate the ability in address operation by introducing two appendage Transistors in the Pull-down aisle for abbreviation leakages. Due to this Stack Transistors the ability amusement has bargain from 18 % in allegory to Accepted 6T SRAM cell. The 8T SRAM provides ability able solution. There is additionally advance in the adjournment in case of 8T SRAM corpuscle is 29% faster as compared to the accepted SRAM cell. So the anew advised low ability SRAM corpuscle absorb bottom ability and can be said that it is a ability acquainted corpuscle which is adequate in today’s VLSI architectonics market.


[1]International Technology Roadmap for Semiconductors.[Online].Available:

[2] Mohammad Sharifkhani, Member, IEEE, and Manoj Sachdev, Senior Member, IEEESegmented Basic Arena Architectonics for Low-Power Embedded SRAM IEEE transaction on actual ample calibration integration(VLSI) systems, vol. 15, no. 2, february 2007

[3] Mai, K.W., Mori, T., Amrutur, B.S., Ho, R., Wilburn, B., Horowitz, M.A., Fukushi, I., Izawa, T. and Mitarai, S. (1998), “Low ability SRAM architectonics application half-swing pulsemode techniques”, IEEE J. Solid-State Circuits, Vol. 33, pp. 1659-71.

[4]Vkita, M. et al. (1993), “A single-bit band cross-point corpuscle activation (SCPA) architectonics for ultra-low ability SRAM’s”, IEEE J. Solid-State Circuits, Vol. 28, pp. 1114-8.

[5]Low-Power SRAM Architectonics Application Half-Swing Pulse-Mode Techniques Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, and Shin Mitarai IEEE account of solid accompaniment circuits, vol. 33, no. 11, november 1998

[6] Gholamreza Karimi1 and Adel Alimoradi “Multi-Purpose Address to Decrease Leakage Ability in VLSI Circuits” Canadian Account on Electrical and Electronics Engineering vol. 2, no. 3, March 2011.

[7] Shin-Pao Cheng and Shi-Yu Huang “A Low-Power SRAM Architectonics Application Quiet-Bitline Architecture”Proceedings of the 2005 IEEE International Workshop on Anamnesis Technology, Design, and Testing, 2005.

[8] Gu Ming Yang Jun, Xue Jun. “Low Ability SRAM Architectonics Application Allegation Administration Technique”,IEEE, 2005.

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